The present application relates generally to semiconductor devices, and particularly to vertical field effect transistors (VFETs) and their methods of fabrication.
Fully-depleted devices such as fin field effect transistors (FinFETs) are candidates to enable scaling of next generation gate lengths to 14 nm and below. Fin field effect transistors (FinFETs) present a three-dimensional architecture where the transistor channel is raised above the surface of a semiconductor substrate, rather than locating the channel at or just below the surface. With a raised channel, the gate can be wrapped around the sides of the channel, which provides improved electrostatic control of the device.
The manufacture of FinFETs typically leverages a self-aligned process to produce extremely thin fins, e.g., 20 nm wide or less, on the surface of a substrate using selective-etching techniques. A gate structure is then deposited to contact multiple surfaces of each fin to form a multi-gate architecture.
Vertical FETs are devices where the source-drain current flows in a direction normal to the substrate surface. In vertical FET devices, the fin defines the transistor channel with the source and drain regions located at opposing (i.e., upper and lower) ends of the fin.
A challenge associated with a vertical FET architecture is precise control of the channel length across a plurality of fins. The channel length is typically defined by etch back of the gate conductor. However, the removal rate of the gate conductor can vary spatially across a substrate due to local variability in pattern density and associated loading effects. Accordingly, it would be advantageous to provide a robust, vertical FET manufacturing process and associated structure that are compatible with existing circuit designs, while enabling precise dimensional control of the channel.